The speed and data path width of microprocessors is continually increasing. As processor performance has increased, memory access has become a bottleneck to overall system performance. Use of cache memory is one way to speed memory access.
A cache memory is a memory that is located functionally between a processor and main memory. The cache memory is generally faster but smaller than main memory. The cache memory decreases effective memory access time by storing copies of portions of the contents of main memory. When a local processor performs certain "cachable" operations requiring memory access, the cache memory is checked first to determine if it contains a copy of the information to be accessed. If so, the processor will perform the operation using the cache memory without accessing main memory. A cache "hit" occurs when the information to be accessed by a cachable operation is stored in the cache memory; a "miss" occurs when the information is not stored in the cache memory.
A cache memory may also be accessed by operations originating other than in a local processor, such as by operations relating to updating main memory or updating other caches, or by operations resulting from requests from other processors in multiprocessor systems. In each case of cache memory access, a cache "hit" or "miss" must first be determined.
For purposes of cache organization, main memory addresses are typically divided into two or three fields. The highest order field is used as a tag comparison field. The next lower order field is used as a cache address field to address a cache tag memory and the cache memory itself. The lowest order field, if any, is used to specify locations within a block of cache memory.
When the contents of a given main memory address are copied to the cache memory, they are copied to the cache address given by the cache address field of the main memory address. The tag comparison field of the main memory address is written as an "address tag" to the cache tag memory at the same cache address. Along with the address tag, a state tag and error detection and/or correction bit(s) may be written to the cache tag memory at the same cache address. The address tag, together with an associated state tag and any error detection/correction bit(s) form a "cache tag."
To determine if the contents of a given main memory address are stored in the cache, the cache address field of the given main memory address is asserted on the address lines of the cache tag memory. In response, the cache tag memory returns the cache tag stored for that cache address. If the address tag of the returned cache tag matches the tag comparison field of the given main memory address, and if the state tag shows an appropriate state and the error bit(s) indicates no error, a hit is indicated.
If the contents of the cache tag memory become corrupted, cache memory accesses that should miss may hit, resulting in potentially disastrous processing errors. To avoid false hits and other serious errors, some method of error checking is generally performed over the address tag and state tag. A parity bit may be used, for example, to detect single bit errors. Error detection and correction (EDC) codes may also be used to both detect and correct errors.
A one-bit cache tag memory error is efficiently detected by use of a single parity bit. But if a single parity bit is used for error detection, no error correction is possible, and a fatal error generally must be returned whenever an error is detected, requiring shut-down and re-initialization of the system. When a cache tag memory error is detected with EDC, certain errors may be corrected, avoiding a system shut-down, but the generation and checking of EDCs can slow down routine cache memory access significantly.